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Honored Contributor
Honored ContributorLatch inference is Quartus bug or specified VHDL behaviour?
Hello,
does anybody know, why Quartus infers latches for the below combinational function if we use an initial value expression for the variable definition of mirrored_data? I looks like a Quartus bug at first sight, because all output bits are actually defined, there's nothing to be latched. The latches are generated for the function result. If you register y in the upper level, the problem disappears. The problem is originated from this Edaboard discussion: http://www.edaboard.com/thread273938.html Best regards, FrankLIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY test IS
GENERIC (
size: integer :=7);
PORT (
x: IN UNSIGNED( size DOWNTO 0);
a: IN INTEGER RANGE 0 TO size;
b: IN INTEGER RANGE 0 TO size;
y : OUT UNSIGNED (size DOWNTO 0));
END;
ARCHITECTURE FLOW OF test IS
function mirror ( data : unsigned ; top : integer ; bottom : integer ) return unsigned is
-- Using an initial value expression in this place causes latch inference, why?
-- variable mirrored_data : unsigned ( data ' range ) := data;
variable mirrored_data : unsigned ( data ' range );
begin
mirrored_data := data;
for index in 0 to data ' length - 1 loop
if (index <= top) and (index >= bottom) then
mirrored_data ( index ) := data ( top - index + bottom ) ;
end if ;
end loop ;
return mirrored_data ;
end function mirror ;
BEGIN
y <= mirror ( x , a , b ) ;
END FLOW;
