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Altera_Forum's avatar
Altera_Forum
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16 years ago

Large Multiplexer fitting problem

Hello, I am implementing a reconfigurable architecture with a reconfigurable interconnection structure to be mapped into a stratix II fpga, the main problem i am having is when i try to fit the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

1 - Is the logic clocked? If so, can you pipeline the MUX into several stages?

2 - You can use design partitioning to reduce your compile time.

3 - Faster machine. This can make a HUGE difference. I had one design that took 45 minutes on a single core machine and 12 minutes on a dual-core.

Jake