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Altera_Forum's avatar
Altera_Forum
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15 years ago

Large delay through IO_OBUF

I am having a problem meeting timing for a SPI interface that talks to an ADC. When I looked at the failing path in timequest, one thing that jumped out at me was this HUGE delay when my internal clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Apologies, I thought you were sending configuration data to ADC.

If you are clocking from fpga to get ADC data remember your interface is no longer the classic source synchronous since data is opposite clock. I have never seen any altera example in this situation but it needs extra care to set delays...