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Altera_Forum
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10 years ago

Large clock skew

Hi, I have a serial signal entering my FPGA. It's generated by a 60MHz clock on another, off-board component. It's latched in by a 240MHz clock in my FPGA, generated by a PLL. However, in Timeq...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks Rysc. I'm going to add a PLL to the 240MHz and phase shift it back to see if that allows me to resolve my timing issue.