Just start learn using ModelSim-Altera for simulation

In my experience;

1) Use Modelsim to perform detailed functional simulation on individual components, and on your hierarchical systems. You can use code coverage and more advanced features to ensure your design is well tested.

2) Synthesize using Quartus with complete timing constraints (SDC) for your design. If your timing constraints are implemented correctly, and the synthesized design passes timing, then it will work in hardware.

3) On rare occasions a timing simulation can help locate an error. However, I cannot think of one case where I have used timing simulation to track down a bug in at least 10 years.

For timing simulation, if the generated .vho file has the same top-level ports as your entity, then you can just recompile the .vho in place of your .vhd and pass the -sdf argument to vsim (-sdftyp, min and max).

Cheers,

Dave

Thanks very much, Dave. Since I just start so there are some problems which confused me.

I know when we want to simulate a design in ModelSim, we should build a library, but when I run the ModelSim-Altera, there are large amount of built library like "cyclone", ''hardcopyii'', so what are these libraries used for?

Another question is: if I don't call Modelsim-Altera 6.5b from Quartus II, I finished my design in QuartusII firstly, then how can I do timing simulation (Gate level simulation) in ModelSim? Which files are need? I read the short tutorial with ModeSim-Altera, but it seems didn't give an example to do that. When I wrote a testbench with Verilog, should is be a .vo file?

Thanks very much. Have a good day.

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I know when we want to simulate a design in ModelSim, we should build a library, but when I run the ModelSim-Altera, there are large amount of built library like "cyclone", ''hardcopyii'', so what are these libraries used for?

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When Quartus writes out a post-synthesis netlist, that netlist contains device specific VHDL or Verilog models so that Modelsim can simulate the netlist. Its those models that are contained in those libraries, and that is why the libraries are named after devices.

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Another question is: if I don't call Modelsim-Altera 6.5b from Quartus II, I finished my design in QuartusII firstly, then how can I do timing simulation (Gate level simulation) in ModelSim? Which files are need? I read the short tutorial with ModeSim-Altera, but it seems didn't give an example to do that. When I wrote a testbench with Verilog, should is be a .vo file?

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vlog file.vo

will compile the netlist

vlog file_tb.v

will compile your testbench, and

vsim -t ps -sdftyp<args> file_tb

will run your testbench. I forget the args to sdf, its something like the hierarchy name of your device under test, and then the sdf filename. The help in Modelsim will tell you.

Cheers,

Dave

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When Quartus writes out a post-synthesis netlist, that netlist contains device specific VHDL or Verilog models so that Modelsim can simulate the netlist. Its those models that are contained in those libraries, and that is why the libraries are named after devices.

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Thanks very much, Dave. So If I use ModelSim PE instead of ModelSim-Altera, there will be no libraries for Altera's devices in ModelSim. I need to load the libraries by myself, right? Sorry to ask these stupid questions:(

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If I use ModelSim PE instead of ModelSim-Altera, there will be no libraries for Altera's devices in ModelSim. I need to load the libraries by myself, right?

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Yep. Its not that hard though. You need to compile the source provided by Altera into a library, but you only need to do that once.

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Sorry to ask these stupid questions:(

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They're not stupid. They're time-saving :)

Cheers,

Dave

Here you'll find a pair of TCL scripts to compile Altera's libraries into a normal ModelSim instalation.

http://www.altera.com/support/examples/tcl/tcl-modelsim.html