Just start learn using ModelSim-Altera for simulation

In my experience;

1) Use Modelsim to perform detailed functional simulation on individual components, and on your hierarchical systems. You can use code coverage and more advanced features to ensure your design is well tested.

2) Synthesize using Quartus with complete timing constraints (SDC) for your design. If your timing constraints are implemented correctly, and the synthesized design passes timing, then it will work in hardware.

3) On rare occasions a timing simulation can help locate an error. However, I cannot think of one case where I have used timing simulation to track down a bug in at least 10 years.

For timing simulation, if the generated .vho file has the same top-level ports as your entity, then you can just recompile the .vho in place of your .vhd and pass the -sdf argument to vsim (-sdftyp, min and max).

Cheers,

Dave