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I know when we want to simulate a design in ModelSim, we should build a library, but when I run the ModelSim-Altera, there are large amount of built library like "cyclone", ''hardcopyii'', so what are these libraries used for?
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When Quartus writes out a post-synthesis netlist, that netlist contains device specific VHDL or Verilog models so that Modelsim can simulate the netlist. Its those models that are contained in those libraries, and that is why the libraries are named after devices.
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Another question is: if I don't call Modelsim-Altera 6.5b from Quartus II, I finished my design in QuartusII firstly, then how can I do timing simulation (Gate level simulation) in ModelSim? Which files are need? I read the short tutorial with ModeSim-Altera, but it seems didn't give an example to do that. When I wrote a testbench with Verilog, should is be a .vo file?
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vlog file.vo
will compile the netlist
vlog file_tb.v
will compile your testbench, and
vsim -t ps -sdftyp<args> file_tb
will run your testbench. I forget the args to sdf, its something like the hierarchy name of your device under test, and then the sdf filename. The help in Modelsim will tell you.
Cheers,
Dave
Honored Contributor
