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Altera_Forum's avatar
Altera_Forum
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16 years ago

JTAG Speed

Hello,

I'm using Quartus II 9.0 to build a CPLD MAX II bitstream. I need a svf output file that is different in function of the JTAG speed. But by default the speed is set to 10 Mhz. As I do not used a Altera Probe but a program in a microprocessor to program the CPLD by JTAG, I can't go higher than 1Mhz. Is there a way to configure that speed in Quartus II environement ?

Thank you in advance for your help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    QUARTUSII

    File>Covert programming files>options>Divide clock frequency by

    select a value between 10 and 16 to have a speed b/w .625Mhz to 1 Mhz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The maximum speed setting in a svf-file can be edited by a FREQUENCY statement. Of course a JTAG programmer is free to use a lower speed anyway. So what's the problem, exactly?