JTAG chain - unable to read device chain

Hi,

Please review the board connections as per the guidelines given in the Cyclone V Pin Connection Guildelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

There are some recommendations in the below Knowledge base:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03312011_647.html

Additional support:

Forum query:

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Unable-to-scan-device-chain-Max-10/m-p/1223132#M18653%3Fwapkw=unable%20to%20read%20device%20chain

Please let us know your findings.

Regards.

Hi Nick,

Is there any update to your issue?

Please check following things on the board:

1) Whether all the power supplies reach upto their recommended levels before configuration starts.

2) Monitor nSTATUS pin. Expected to be low until the power supplies are stable.

3) If the power supplies are stable then are nSTATUS and nCONFIG pins going high. You should see these pins to remain in high state during configuration.

4) Is there any broken link in the daisy chain of the FPGA devices and the JTAG.

If possible please share a block diagram of how the devices are connected in chain and to the JTAG ports.

Regards.