Forum Discussion
Ash_R_Intel
Regular Contributor
5 years agoHi Nick,
Is there any update to your issue?
Please check following things on the board:
1) Whether all the power supplies reach upto their recommended levels before configuration starts.
2) Monitor nSTATUS pin. Expected to be low until the power supplies are stable.
3) If the power supplies are stable then are nSTATUS and nCONFIG pins going high. You should see these pins to remain in high state during configuration.
4) Is there any broken link in the daisy chain of the FPGA devices and the JTAG.
If possible please share a block diagram of how the devices are connected in chain and to the JTAG ports.
Regards.