Honored Contributorhi
i have made an jtag interface because i want to program an altera max 3000. The quartus programmare show me a generic error "unknown integrity checking failure". where do i start for debug and solve my problem? what test can i do? have you a schematic for max 3000 connection with jtag? thank's and sorry for my english, i'm italian!!!
Honored ContributorHonored Contributoryes, it is compatible!!
the schematic is the same that you can find in the byteblasterMV datasheet thank's for respondingHonored ContributorYes, it should work. The MAX3000 JTAG connection is identical to FPGA:
TCK with pull-down, TMS and TDI with pull-up, TDO, VCC and GND.Honored Contributori haven't made the pull up and pull down resistor!!! i have simply connect the pin of the cpld with the corresponding pin of the jtag!!!could this be the cause?
thank'sHonored ContributorParticularly missing or too high resistance TCK pull-down is often causing problems. Some Altera devices have an additional internal weak pull-down resistor, but it's not said in the MAX 3000 datasheet.
Honored ContributorOK
i try to add the resistor (1k for pull down and 10k for pull up, right?). i tell you about!!! thank's p.s. sorry for the time, but i think we have different time zonesHonored ContributorHonored Contributorif i could i'll kiss you!!!:)
that's all right, it works!!! thank you so mutch see you soon
