Hi Jim,
You mentioned this Bug ID 543053, are you referring to this KDB information?
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2018/how-do-i-enable-micron-s-mt25q-support-for-eol-of-epcq---256mb--.html
Did your processor set the correct NVCR value into the MT25QU flash device before writing the .rpd file? As explained in Bug ID 543053, the MT25QU have a non-volatile configuration register (NVCR). The NVCR must be set to an appropriate value according to the MT25Q device and configuration mode in FPGA device families. For Arria 10 the dummy clock cycles is 10 and require to use 4 byte addressing mode.
The default generated .rpd file from Quartus tools is little endian format. By default the programming the .jic/pof file, the Quartus programmer will perform the bit swapping (LSb first) before writing the data into the EPCS/EPCQ/EPCQA device. Thus you need to perform the bit swapping when using the little endian .rpd file before writing the data into MT25QU device. If you set the big endian option in the Convert Programming File tools when generating the .rpd file, then you don’t require to perform the bit swapping since the generated .rpd file is in big endian format.
Regards,
Nooraini