Altera_Forum
Honored Contributor
17 years agoJIC file creation for CFI Flash
A similar question was asked not too long ago for a EPCS device. Here is my hardware configuration:
CycloneII (with Nios) and MaxII sharing parallel CFI Flash (256MB) addr/data bus. MaxII contains PLF (parallel flash loader) design and will configure CycloneII using 1-bit passive serial. The Flash is designed to be partitioned to have a default HW image (pg0 - 0x1900000) and a user defined HW image (pg1 - 0x1C80000), similarly a default SW image (pg0 - 0x0) and user defined SW image (pg1 0x07E0000). The MaxII is setup by default to configure the FPGA from the default location stored in Flash. Once the HW image is loaded, I believe the SW image gets copied from Flash (NIOS memory mapped to 0x0) and stored into SDRAM (NIOS memory mapped to 0x02000000). The part i'm trying to get working is actually programming the flash. Right now I just want to get the default HW and SW images programed into flash by means of JTAG connected to CycloneII. Using the Quartus programming tool to load the factory default PFL into the CycloneII to write to CFI Flash. The files i'm starting with are .SOF (HW) and .ELF (SW). This is where i'm stuck, how do I get these files into the correct format to input into the "Convert Programming Files" tool to create my JIC output? I tried using these SDK shell commands to create a .hex file, but the 2nd command is giving me "interleave must be positive" errors: elf2flash --base=0x0 --end=0x7DFFFF --reset=0x02000000 --boot=boot_loader_cfi.srec --input=sw.elf --output=sw.flash nios2-elf-objcopy –input-target srec –output-target ihex sw.flash sw.hex Thanks, Andy