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Honored Contributor
Honored Contributor"j" is not a constant in verilog for loop addition
Hello, I am trying to make a simple for loop to add up a parameterizable count of numbers, all in the same clock cycle( I am aware that this may not fit in a single cycle, I may split it up lat...
Altera_ForumHonored Contributor
Honored Contributorrozatib
Verilog specifies that if you are taking a slice, one of the indices must be a constant.
