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Altera_Forum
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13 years ago

ITB clock lines -- clk share between blocks : How ?

Hi On Stratix IV GX230 board, I would like to use REFCLK_R5 (pins: G1, G2, on transceiver block BankQR2) to drive REFCLK_R1 (pins: AL1, AL2, on transceiver block BandQR0). Stratix IV handboo...
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Altera_Forum
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13 years ago

Thanks genoli !

It is very helpful.

Though we meet another problem now.

Before we can use Quartus fitter, the project has to be analysis&synthesis , where we meet analysis&synthesis error,

"Error (10650): Verilog HDL Display System Task at altpll_0.v(213): The width_clock of 7 specified is not supported in STRATIXIV

Error (12152): Can't elaborate user hierarchy "jesdcon_a:u_jesdcon_a|altpll_0:the_altpll_0"

"

-- but this is totally another problem.