Honored Contributor
Honored ContributorThe warnings I have now are:
Analysis & Synthesis: Warning (10492): VHDL Process Statement warning at prova1.vhd(39): signal "nombre" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Fitter: Warning: Feature LogicLock incremental compilation is not available with your current license Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details In EDA and in Simulations there are no errors nor warnings. I set reset 1 from the begining of simulation, during a clock period. then it remains 0 until the end. I generated the clock using the menu clock, as you've said.
