It adds 3 and subtracts 1 instead of adding just 1

The clock comes from a pin: I assigned to the corresponding input pin. This clock it is working at 50MHz, so the period it is 20ns.

Indeed there where a lot of warnings on Timing Analysis due to pulse width violations.

I set Classical timing Analyzer on timing settings. I added clk as a system clock and I fixed 50MHz as the maximum frequency. Now there are no warnings on Timing, but the simulation is still wrong.

The other time I used Quartus, I had also timing warnings, but the simulations were ok... I realize that I don't know a lot about timing settings...

Now I have three warnings on all compilation,

1. On Analysis and Synthesis: 'nombre' is not on sensitivity list and is read indise the process. But I understood the reasons.

2. On Fitter: Logiclock incremental not available: my license is from web edition, ok

3. On Fitter: some pins have incomplete I/O assignments. I assigned my three pins to the clock, a button and a LED.

Any idea why the simulation it's still wrong?

Thanks!!