It adds 3 and subtracts 1 instead of adding just 1

In my opinion there is a mistake somewhere in your reason.

Most of all the code seems ok, but:

1- as mmTsuchi told you, in a synchronous process's sensitivity list you need to put only reset and clock signal.

2- your signal is too long and will be synthetized away because you use it only through bit 0 and bit 4.

so define it as:

signal nombre : std_logic_vector(4 downto 0):=b"10101";

3- told that how are you looking at the signal output?

You've the out on a pin and you see it with an external digital scope?

Or it is only something in the simulator?

I ask because simulator can change the polarity of the signal.

Moreover you could have some timing problem.

If it's the case and you're looking at it in the simulator try to simulate it only in functional and not in timing (if the result change, your timing problem are true).

4- How fast is your clock?

you think to read:

signal your output

10101 0 (because you reset the DFF at the beginning)

10110 1

10111 1

11000 1

11001 1

11010 1

11011 1

11100 1

11101 1

11110 1

11111 1

00000 0

00001 0

00010 0

00011 0

00100 0

00101 0

00110 0

00111 0

01000 0

01001 0

01010 0

01011 0

01100 0

01101 0

01110 0

01111 0

10000 1

10001 1

10010 1

10011 1

10100 1

10101 1

and cyclically the same, right?

you see a sort of square wave that has an initial phase shift compared to the started reset signal.