Forum Discussion

Honored Contributor

13 years ago

Issues with making a pipeline register in VHDL

I am currently having an issue with making a pipeline register in VHDL. A pipeline register is simply a register that connects two portions of a CPU pipeline together. It is easier to explain in code then on text in terms of its functions, so here is the code.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IF_to_ID_registers is
port (
      
	   fetched_instruction : in std_logic_vector(31 downto 0);
		
		clear: in std_logic;
		writeregister : in std_logic;
		send_zeros_instead : in std_logic;
		
		clk : in std_logic;
		
		output_instruction : out std_logic_vector(31 downto 0)
		
     );
end IF_to_ID_registers;
architecture Behavioral of IF_to_ID_registers is
signal instruction_register : std_logic_vector(31 downto 0); -- The internal register
begin
process(fetched_instruction, writeregister, clk, send_zeros_instead)
begin
if ( clk = '0' AND writeregister = '1') then 
instruction_register <=  fetched_instruction; -- Write the value into the register
end if;
if (rising_edge(clk)) then
if (send_zeros_instead = '1') then
output_instruction <= (others => '0');  -- Output zeros instead
else
output_instruction <= instruction_register; -- Output the register 
end if;
end if;
if (clear = '1') then  
instruction_register <= (others => '0');  -- Clear the register
end if;
end process;
end Behavioral;

The issue I have with this code is that during compilation I get the following error messages.


Warning (10492): VHDL Process Statement warning at PipelineRegisters.vhd(42): signal "clear" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at PipelineRegisters.vhd(25): inferring latch(es) for signal or variable "instruction_register", which holds its previous value in one or more paths through the process
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled

I am wondering what I did wrong. It seems like the issue stems from the instruction_register signal, but I cant tell what the issue is.

43 Replies

Altera_Forum
Honored Contributor
13 years ago
To get rid of latches use clocked process for all your logic.
process(clk)
if rising_edge(clk) then
do this
do that
etc
end if;
end process;
Altera_Forum
Honored Contributor
13 years ago
Hi, have you drawn schematic for that ? It will help you very much.

VHDL needs a few rigor.
I advice you to write two synchronous process which begin by process(clk) (no other signal in sensitivity list)
* one for instruction_register
* the other for output_instruction.

90% of process are process(reset, clk).

if ( clk = '0' AND writeregister = '1') then :eek:

i use pipeline to reduce propagation time of a design, but it increases latencies.

First draw schema
Second, describe it in VHDL. VHDL is a desciption language.
Good work !
Altera_Forum
Honored Contributor
13 years ago
Is there any way then how I can implement the asynchronous clear.
Altera_Forum
Honored Contributor
13 years ago
Just add it before clk edge statement:
process(reset,clk)
if reset then
...
elsif rising_edge(clk) then
...
...
end if;
end process;

Altera_Forum

Honored Contributor

13 years ago

Ok I tried doing it somewhat and now I have this issue:


Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10029): Constant driver at PipelineRegisters.vhd(51)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (10028): Can't resolve multiple constant drivers for net "instruction_register" at PipelineRegisters.vhd(45)
Error (12152): Can't elaborate user hierarchy "IF_to_ID_registers:inst10"
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 5 warnings
	Error: Peak virtual memory: 357 megabytes
	Error: Processing ended: Tue Jul 24 15:22:46 2012
	Error: Elapsed time: 00:00:02
	Error: Total CPU time (on all processors): 00:00:02

My new code is:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IF_to_ID_registers is
port (
      
	   fetched_instruction : in std_logic_vector(31 downto 0);
		
		clear: in std_logic;
		writeregister : in std_logic;
		send_zeros_instead : in std_logic;
		
		clk : in std_logic;
		
		output_instruction : out std_logic_vector(31 downto 0)
		
     );
end IF_to_ID_registers;
architecture Behavioral of IF_to_ID_registers is
signal instruction_register : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
if (send_zeros_instead = '1') then
output_instruction <= (others => '0');
else
output_instruction <= instruction_register;
end if;
end if;
end process;
process(clear)
begin
if (clear = '1') then 
instruction_register <= (others => '0');
end if;
end process;
process(writeregister, fetched_instruction)
begin
if ( clk = '0') then 
if (writeregister = '1') then
instruction_register <=  fetched_instruction;
end if;
end if;
end process;
end Behavioral;

Altera_Forum
Honored Contributor
13 years ago
I believe your issue is that you have two processes trying to drive the instruction_register. Try making one process to both clear and write to the instruction_register.
Altera_Forum
Honored Contributor
13 years ago
Indeed, you are not allowed to drive a node from more than one assignment. You can view a process as one assignment and you can assign within one process in several statements depending on logic that decides the drive sequence. But assigning to same node in two processes does not tell the compiler how is that drive going to take place.

Altera_Forum

Honored Contributor

13 years ago

Ok, now I tried this:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IF_to_ID_registers is
port (
      
	   fetched_instruction : in std_logic_vector(31 downto 0);
		
		clear: in std_logic;
		writeregister : in std_logic;
		send_zeros_instead : in std_logic;
		
		clk : in std_logic;
		
		output_instruction : out std_logic_vector(31 downto 0)
		
     );
end IF_to_ID_registers;
architecture Behavioral of IF_to_ID_registers is
signal instruction_register : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
if (send_zeros_instead = '1') then
output_instruction <= (others => '0');
else
output_instruction <= instruction_register;
end if;
end if;
end process;
process(clear, writeregister, fetched_instruction)
begin
if (clear = '1') then 
instruction_register <= (others => '0');
end if;
if ( clk = '0') then 
if (writeregister = '1') then
instruction_register <=  fetched_instruction;
end if;
end if;
end process;
end Behavioral;

I got these warnings:


Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled

Can somebody help me? I am already a few days back from this problem.

Altera_Forum
Honored Contributor
13 years ago
You still haven't implemented all your assignments on clock edge.
Why do you have one clocked process for output_instruction but you left the poor instruction register in a latching process. Just push it up into the clocked process.
Altera_Forum
Honored Contributor
13 years ago
So everything has to be on one of the two clock edges?

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Issues with making a pipeline register in VHDL

43 Replies

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