Issue while Simulating Nios II Embedded Processor Designs

Hello,

I figured out the way to test another simple design (which has a top level module connected with a counter) as per the altera wiki page:

http://www.alterawiki.com/wiki/simulating_designs_with_lower-level_qsys_systems

So I guess that should be okay. Please discard my above question.

Thank You,

Akhil

Hi there,

The problem would probably occur when the full path for "../_primary.vhd" is too long. Try to save the whole project under C:\ root directory or somewhere with a shorter path to solve the problem.

Cheers,

Alex

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Hello All,

I was following the example from Altera at the link: http://www.altera.com/literature/an/an351.pdf

for a QSYS simple system simulation. I generated the testbench from QSYS, created a NIOS II SBT eclipse project.

The I built the project, and Right-clicked on hello_world_an351 in Project Explorer. Pointed to Run As, and then clicked Nios II ModelSim.

After some time, the ModelSim gets launched and the commands run. However after running and building some modules properly, I am getting an error log

from ModelSim:

# ** Error: (vlog-7) Failed to open file "C:\altera\All_Projects\D13_QSYS_Testbench_Ex_from_Altera\an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor\libraries\niosii_system_tb_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/altera_avalon_sc_fifo/_primary.vhd" in w+b mode.

# No such file or directory. (errno = ENOENT)

# ** Error: (vlog-7) Failed to open library file "C:\altera\All_Projects\D13_QSYS_Testbench_Ex_from_Altera\an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor\libraries\niosii_system_tb_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/altera_avalon_sc_fifo/_primary.vhd" in read/write mode.

# No such file or directory. (errno = ENOENT)

# ** Error: C:/altera/All_Projects/D13_QSYS_Testbench_Ex_from_Altera/an351_design/niosii_system/testbench/niosii_system_tb/simulation/submodules/altera_avalon_sc_fifo.v(879): Verilog Compiler exiting

I had been trying to fix this, however could not find much clues. Is anyone aware of this error? If so, please help me out here.

That would be a big help.

Thank You,

Akhil

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Akhil Hi,

Did you mange to solve this problem?

I am facing this problem too.

THX,

Guy.