Forum Discussion

Honored Contributor

12 years ago

Issue while Simulating Nios II Embedded Processor Designs

Hello All, I was following the example from Altera at the link: http://www.altera.com/literature/an/an351.pdf for a QSYS simple system simulation. I generated the testbench from QSYS, created...

Altera_Forum

Honored Contributor

12 years ago

Hello,

I figured out the way to test another simple design (which has a top level module connected with a counter) as per the altera wiki page:

http://www.alterawiki.com/wiki/simulating_designs_with_lower-level_qsys_systems

So I guess that should be okay. Please discard my above question.

Thank You,

Akhil

Forum Discussion

Issue while Simulating Nios II Embedded Processor Designs

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