jrrguzman
Occasional Contributor
Occasional ContributorIssue when manually instantiating clock buffers in Arria 10
Hi, I'm using a signal which is used in the design as logic and as clock (at separate locations). If I just run the design flow, Quartus (Prime Standard 17.0) is able to instantiate a clock buffer ...
Hi all,
I figured out the issue: The signal that I'm trying to buffer comes from a LVDS input and I do not instantiate the differential input buffer manually. At this point if I run the fitter-placement, it seems the clock buffer is placed before the inferred differential input buffer and it makes the fitter fail miserably because it can't find the signal, although synthesis has already inferred the LVDS input buffer. (@GNg Maybe something you should consider fixing for next Quartus releases).
To work-around that, I had to manually instantiate the differential input buffer ussing the ALTERA primitive: ALT_INBUF_DIFF. With that in place Quartus does not complain and gets me a clean implementation.
Cheers
