Contributor
Super ContributorWhen you generate a system in Platform Designer, the main output is the HDL files that define the interconnect and the components that connect to it. It's in the folder named after the system. This HDL should already include the addressing in it and includes a top-level file for instantiating the system into a higher-level design. What do you need the separate HDL you mention for?
#iwork4intel
ContributorThe VHDL written FPGA fabric master has multiple AvalonMM master ports that are connected to multiple peripherals which are shared with a Nios that also connects to them. When the FPGA fabric master wants to perform a read/write it shall take the base address of the desired peripheral and add the offset for the register to be accessed. This information is available to the Nios from System.h file. How does a fabric based master get it? The base addresses should exist in a VHDL package version of the System.h which can be included into the VHDL of the custom fabric master. I hope it is more clear why I need this.
In Qsys we have a tab for "address map". I just need this information to be put into a VHDL package automatically when compilation starts!
ContributorIntel provides no solution for this.
