Is there a plan to fix VHDL code of Cyclonev_atom? it contain plenty of errors.

Hi,

I cannot reproduce the error. Running vcs tb_cyclonev_termination gives error below:

*** Using c compiler gcc instead of cc ...

Chronologic VCS (TM)

Version N-2017.12-SP2-4_Full64 -- Wed Jul 10 16:17:58 2019

Copyright (c) 1991-2017 by Synopsys Inc.

ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement

controlling such use and disclosure.

Top Level Modules:

tb_cyclonev_termination

Warning-[ELW_UNBOUND] Unbound component

The component instantiation

'/\/tb_cyclonev_termination/cyclonev_termination\/INST' (file:

/folder/stam.vhd, line: 82) will

have no effect because component 'CYCLONEV_TERMINATION_ENCRYPTED' is

unbound. No entity definition for component 'CYCLONEV_TERMINATION_ENCRYPTED'

can be found in the following libraries ( WORK ) referenced by the

architecture 'BEHAVIOR' of entity 'CYCLONEV_TERMINATION'.

Please bind the component explicitly to an entity (architecture) pair, and

verify that the pair was analyzed successfully.

TimeScale is 1 s / 1 ns

Warning-[TFIPC] Too few instance port connections

t.v, 3

"cyclonev_termination cyclonev_termination();"

The above instance has fewer port connections than the module definition.

Please use '+lint=TFIPC-L' to print out detailed information of unconnected

ports.

Note-[SIMU-RESOLUTION] Simulation time resolution

Simulation time resolution is 1 NS

Starting vcs inline pass...

2 modules and 0 UDP read.

However, due to incremental compilation, no re-compilation is necessary.

make: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

make[1]: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so

make[1]: warning: Clock skew detected. Your build may be incomplete.

make[1]: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

ld -shared -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o

rm -f _csrc0.so

make[1]: warning: Clock skew detected. Your build may be incomplete.

if [ -x ../simv ]; then chmod -x ../simv; fi

g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-E -Wl,-rpath=/tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib -L/tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib _1668_archive_1.so _prev_archive_1.so _csrc0.so SIM_l.o _csrc0.so rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o linux64_scvhdl_0.so vh/scscomm.o vh/scsFilelist.o -lzerosoft_rt_stubs -lerrorinf -lsnpsmalloc -lvfs -lvirsim -lvcsnew /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_main.o -lvcsmx -lreader_common /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/libBA.a -lsimprofile -luclinative /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_tls.o -Wl,-whole-archive -Wl,-no-whole-archive /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl

../simv up to date

make: warning: Clock skew detected. Your build may be incomplete.

CPU time: .385 seconds to compile + .014 seconds to elab + .231 seconds to link

Thanks.

Best regards,

YY