Is there a plan to fix VHDL code of Cyclonev_atom? it contain plenty of errors.

Sure.

1. Strip the definitions of entity cyclonev_termination and of entity cyclonev_termination_logic from the full file:

(Please change path of $Quartus_ROOTDIR , to match your installation of quartus_18.0.0.614)

%sed -n '6482,6599p;6599q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > stam.vhd

​

%sed -n '6421,6481p;6481q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > stam2.vhd

2.Create this t.v Verilog file

module tb_cyclonev_termination();

cyclonev_termination cyclonev_termination ();

endmodule

module tb_cyclonev_termination_logic();

cyclonev_termination_logic cyclonev_termination_logic ();

endmodule

3.Run these VCS commands:

%vlogan t.v

%vhdlan stam.vhd sta2.vhd

%vcs tb_cyclonev_termination

You will get 4 errors of Error-[BADFORMALSPEC] Bad formal part specified, one error of Error-[ANALERR_SIZEMISMATCH1] Size mismatch, one error of Error-[ANL-PORTDI-ERR] Port direction mismatch

Now run this command

%vcs tb_cyclonev_termination_logic

You will get two errors of type Error-[BADFORMALSPEC] Bad formal part specified