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sYimi's avatar
sYimi
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7 years ago

Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

As the FPGA I/O resource is limited, I translate LVDS signals to single ended type (LVCMOS) by external translator (TI SN65EPT23), and now I want to process the single ended signal with ALTLVDS_RX. U...
sYimi's avatar
sYimi
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7 years ago

In fact, we can use one or two synchronous clock to collect all of the eight channel data.