Is it possible to make the code faster via pipelining?

Indeed as Tricky said you need time and testing to finalise.

But I note your counter though constrained in declaration but not in actual logic, you must define at what value your counter returns back in the logic of counter.

You don't need the loop statement as it is doing nothing and each assignment inside this loop is done once anyway.

May be you can do your testing this way:

instantiate your first working vhdl module and then the new one. Give them same inputs and check outputs until they are same with just delay being different.