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Altera_Forum
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14 years ago

Is it possible to make the code faster via pipelining?

Hi there everyone...i'm trying to implement both TEA and XTEA algorithm to make a comparison. I have a complete working vhdl of TEA as following: Library ieee; use ieee.std_logic_1164.all; use ieee....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi kaz! thank you for your prompt reply! and by constraining the counter as you suggested, the throughput is now 14ns! improved by 1 ns!you're a genius! hahaha:) as for the delay balance...does quartus support this? how can i balance the delay when i don't know the delay of the components? does quartus support "after 3ns" command? anyway i can implementing the delay balancing via coding that you know of? thanx for suggesting the use of signals...i'm looking into it but thanx again for all the advice!