Is it possible to make the code faster via pipelining?

First the counter need be constrained otherwise it defaults to some 40 or so bits (integer limit) and wouldn't come back to zero until it goes that far and that is not what you want.

For pipeline balance you need to match the delay caused by each register so you add or xor data ...etc. as originally designed but with delay. For example

if A = A1+A2 and

C = A + B

then if you delay A you should delay B equally so that A matches B to get correct C.

I said your pieline is incomplete because the path from input to Z to Zeq to Y is all combinatorial. You only pipelined the computation of Z.

May be the best way for you is to use signal instead of variable as then it will force a pipeper assignment and all you need is balance the delays.