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Altera_Forum
Honored Contributor
14 years agohi kaz, thank you so much for the comment! appreciate it...you mentioned that i have to balance out pipeline? sorry but i don't quite understand how i can do so? i'll redesigned the long combinational path part as you mentioned.
on the other hand, will constraining the counter help achieve faster speed? Also, it seems like the code works when i use "use ieee.std_logic_unsigned.all;" but not when i use "use ieee.numeric_std.all". when i use the later package the following error will appear: Error (10327): VHDL error at TEA_en.vhd(46): can't determine definition of operator ""+"" -- found 0 possible definitions you also mentioned that i only have partial pipelinng. how do i achieve a full pipelining? The system block diagram (in fact i used the c code in the following lin to model my system) can be seen here: http://en.wikipedia.org/wiki/tiny_encryption_algorithm Again, thank you for your ideas and comments! they are of great help!:)