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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is it possible to have Toplevel Ports, that are not placed on FPGA IOs?

Is it possible to have ports in the toplevel entity that are not placed in FPGA IO pins? When I leave them unconstrainted, the fitter will choose for me of course. But is there any constraint or attribute, that tells the fitter that a signal should not be placed on an outside IO?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    If you have unused pins top level connections, remove them. They have to be mapped to a pin.

    You may be able to map them to a virtual pin, but this is not meant for this situation, its meant for when you are compiling a block to be integrated into a larger design at a later date.