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It's just basic math..
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indeed. if you look at TQ description of various forms of set_input_delay you will find out that equivalence.
If you draw waveform then it should be obvious:
if tCO max of external device is (n) ns then the target register must anticipate that (n) ns of period will be the max offset between arriving data and its clock relative to latching edge, so target register must have tSU of [period -n] or better(less).
if tCO min of external device is (m) ns then minimum offset is (m) ns relative to previous edge and the target register should have tH of (m) ns or better.
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