Is a Test bench needed for simulation?

Thanks Rochmadp,

I now have a ghetto divider simulated. However, i had to add the inputs manually, which was a rather big pain. I added the the waves I wanted to the vwt file before I exported the vwt file. However, I think I might be doing something wrong on step 3 of your instructions.

When it asks for the name of the Top level design module in the test bench I assumed it was referring to the Entity name , and when it asked for the design instance i put in the architecture name. Did i make the right assumptions, or have i got (yet again) a case of the newb?

Thanks for your help.