Is a Test bench needed for simulation?

You will always need a testbench file. The great thing about testbenches is you can do many many things you couldnt do in synthesizable code, things like time references

eg:

signal clk : std_logic := '0';

clk <= not clk after 10ns; -- a 100MHz clock

nice convoluted wait statements in processes:

eg.

wait until rising_edge(clk) and output_valid = '1';

File IO, especially useful for writing log files:

file op_log : text open write_mode is "mylog.log";
variable opline : line;
...
write(line, string'("HELLO WORLD!"));
writeline(op_log, line);

and then other stuff like pointers, protected types, random number generation and all the signal attributes that can be useful for waiting on (like 'event, 'transaction, 'delayed etc).

Creating a testbench from a waveform file gives you limited scope on what you're actually testing, and normally doesnt give you much scope for full random testing. If you're interested in testbench theory, get hold of a copy of "Writing testbenches: Functional verification of HDL models" by Janick Bergeron. It isnt all in VHDL, but its mostly about the theory of testing and methodologies.