IP Migration of DDIO_IN, DDIO_OUT and SYSCLKPLL from Stratix5 to Cyclone10 GX in Quartus Prime Pro.

The PLL is easy: as stated, you have to delete the PLL from your design and add in the new one. I believe it's named IOPLL Intel FPGA IP.

For the DDIO, a migration flow for exactly what you're doing is described here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf