IP-Based Flow with Qsys & IP Catalog/Parameter Editor

Hello,

Back in the days we used to create custom components with SOPC Builder and added MegaWizard Plug-In Manager generated code such as memories, LVDS SERDES and PLLs to be instantiated in the custom component. We were able to assemble this components in SOPC Builder to create larger systems, generate simulation output and synthesize the system. Life was simple and good.

Fast forward a couple of years. Qsys and IP Catalog/Parameter Editor powered by Qsys are taking over for the new device families like Arria 10. Our IP-based design flow as described above does no longer seem to work. Please have a look at the attached sketch to get an idea of what we want to do.

What we notice when we try to add the IP Catalog generated files to the Qsys component:

• Cryptic folder and file names containing the Quartus II version and a unique (?) identifier. That's a nuisance when using version management systems and switching from one Qartus II version to another.

• A simulation and a synthesizeable version of the macro.

• Simulation libraries other than work in the simulation version. These libraries would have to be passed to the superior Qsys system in one way or the other in order to run a system level simulation. However, Qsys does not seem to provide any mechanism to do so.

Now the question for you: How do you implement the modular or IP-based flow with Qsys when IP Catalog/Parameter Editor generated code is involved? What is the approach that Altera wants the customers to follow? Did Altera think through this at all?

Your ideas and experiences on the topic are very appreciated. Thank you.

Regards,

Thomas

Some notes:

• Our issue is shown with the example of a generated memory. We know that memories can be directly inferred or directly instantiated.

• Routing the memory interface signals to the component and adding a memory in Qsys is not an option as we want to use Qsys for what we believe it was designed: A system integration tool.