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Altera_Forum
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15 years ago

IO Pin status when Power up the Device

I am using Altera Cyclone device & programmed via Quarts II 7.2 to generate square pulse on a IO pin. When i power up the FPGA , IO pin goes momemnty high (180ms). Is there any option in Quarts ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The behaviour is due to FPGA hardware (weak pull-up resistors) and not depending on Quartus. If you think about it, you'll realize, that the configuaration can't have an effect on the device behaviour before it's loaded. You can either change the polarity of your logic signal, or place a pull-down resistor of 1k to override the weak pull-up.