New Contributor
New ContributorI made a very simple new project. The same device (AGFB014R24B2E3V). This is the RTL.
module tri_test (
input logic clk1,
input logic clk2,
input logic en1,
input logic en2,
output logic out1,
output logic out2
);
assign out1 = (en1) ? clk1 : 1'bz;
assign out2 = (en2) ? clk2 : 1'b0;
endmodule
You can see that out1 "should" be clk1 if en1 is high, and Hi-Z if en1 is low. You can also see the post-fit Technology Map Viewer shows the polarity implemented is wrong (there is no inverter added to compensate for the active-low OE on the IO_OBUF primitive).
The out2 circuit is the same logic, but without the tri-state (it just outputs 0 if en2 is low).
The whole project folder is now attached.
Super ContributorHi Rob,
You're absolutely right. Sorry for the confusion before. The post-fit Technology Map Viewer result is totally opposite of the RTL viewer and simulation. I noticed this problem still persists on version 21.3 and above.
I also found out a previous similar issue from KDB here. By right, the problem should be fixed beginning with version 21.3 but looks like it wasn't being solved thoroughly.
At the mean time, I think you can invert the output enable signal in your RTL by using assign out1 = (!en1) ? clk1 : 1'bz;. By doing this, can temporarily get the correct output and post-fit Technology Map Viewer.
I'll reflect this bug to internal team for further investigation.
Thanks,
Best regards,
Sheng
