IO_OBUF polarity not matching RTL

Hi Rob,

I further think about the problem you mentioned and found out should be no problem with both IO_OBUF primitive and RTL.

IO_OBUF primitive is designed to be active low OE means you have to use '0' instead of '1' to enable output in order to enable the clock.

So when using assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz;, an inverter is automatically added to make the RTL matches the IO_OBUF primitive design setting. If change to assign TRIG[0] = (lb_enable_dd) ? 1'bz : clk_fast;, I guess the inverter will most likely disappear. The problem is IO_OBUF OE part there will change based on which RTL you are using to make sure '0' is used to enable output at last.

If you still insist to use '1' for triggering the clock, I think you have to additionally add a not gate or inverter in front of active low OE manually by yourself. O_OBUF primitive setting will not do that for you.

Thanks.

Best regards,
Sheng