IO_OBUF polarity not matching RTL

Yes, I understand driving 0 will instantiate a different buffer. I am using that "version" to show that my logic is sound.

Let me put it more simply. If my RTL contains this line in the top level, and TRIG[0] is defined as an output pin on the top-level design.

assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz;

And lb_enable_dd is "1", what would you expect on the output pin TRIG[0]? I think it should be "clk_fast".

And if lb_enable_dd is "0", I would expect Hi-Z? Does that sound correct?

If so, there is a problem in the way Quartus is synthesizing this statement.

I believe you that IO_OBUF has an active low OE input, I see that in the tech view. However, why is there no inverter instantiated by the tools before the OE# input to match the logic defined in the RTL. This is the issue. What I am coding is not what I am getting, and I have confirmed this on the hardware as well.