New Contributor
New ContributorThat doesn't change the fact that when I implement an active-high tri-state buffer (either with RTL or instantiating a GPIO IP block), the tools put in the IO_OBUF and the polarity of the OE is active-low, but that doesn't seem to be compensated for.
The behavior of my hardware is the opposite of what I have coded for the design and when I drive 0 instead of hi-Z in the "disabled" state the polarity is now correct. I have never actually instantiated an IO_OBUF, that is just what the tools used during synthesis but it seems like they are not compensating for the active-low OE of that primitive.
So...
assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz;
lb_enable_dd = 0, TRIG[0] = clk_fast (observed on the HW, which is wrong, it should be hi-Z)
lb_enable_dd = 1, TRIG[0] = hi-Z (observed on the HW, which is wrong, it should be clk_fast)
assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'b0;
lb_enable_dd = 0, TRIG[0] = 0 (observed on the HW, which is correct)
lb_enable_dd = 1, TRIG[0] = clk_fast (observed on the HW, which is correct)
Thanks
Rob
Super ContributorHi Rob,
In order to be in tri-state mode, you have to drive "hi-Z" instead of "0". Otherwise, it will be switched to a non-tristating output as you say before if you drive "0". Thus, driving "hi-Z" or "0" will result in two different modes.
In tri-state mode, IO_OBUF primitive comes originally with active-low OE internal settings. That is the primary internal logic function of IO_OBUF primitive which you cannot simply change it.
Btw, you can refer to here https://en.wikipedia.org/wiki/Three-state_logic as well for Three-state logic. (Many devices are controlled by an active-low input called OE (Output Enable) which dictates whether the outputs should be held in a high-impedance state or drive their respective loads (to either 0- or 1-level).)
Thanks.
Best regards,
Sheng
