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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

so since no automated check is possible, with every major change in the source code I should have a look if path delays for the SPI buses are similar... not what I was hoping for...

thanks for the answers, they really helped!