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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

O.K., I can understand why. I fear, Timequest isn't prepared for this.

If the logic is simple and not involving a different number of logic cells for individual pathes, the skew can be expected rather small (< 1 ns). If you are using a robust spi timing, there won't be a problem. The most critical parameter would be the SCK to MISO round trip delay.