IO constraints for buses routed through FPGA

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I don't understand why you apparently need a minimum tpd constraint? What's the problem when allowing a delay of 6 to 16 ns (if these are the tpd numbers achieved with various devices you want to use for your design)?

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because I am afraid that delays for individual lines of the bus will be different with 0-10 ns...

with a tpd in range 6-10 I ensure that the signals will have a timing variation at the output of the FPGA of maximum 4 ns... that's how I understand it...