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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I don't understand why you apparently need a minimum tpd constraint? What's the problem when allowing a delay of 6 to 16 ns (if these are the tpd numbers achieved with various devices you want to use for your design)?