IO constraints for buses routed through FPGA

:cry: unfortunately my problem was not so easily solved...

My FPGA is a Cyclone III.

I tried to constrain the delays between some ranges but it's impossible to match constraints for both slow and fast devices :-( in slow devices typical delay is ~14 ns, I tried to set min 14, max 15 to ensure approx the same delay for all bus signals but than it fails with the fast device that can at most delay ~6 ns...

I don't care how much delay I have, I just want to keep the relation between signals the same and for this only setting maximum delay is not enough :cry:

I noticed in TimeQuest that the delays are though similar for all signals for fast and slow devices (+- 200 ps), I could live with this but I need an automated way of checking this...