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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As already mentioned, you would want to specify maximum tpd constraints.

P.S.: (From Rysc's TimeQuest User Guide)

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Combinatorial Paths through Device:

set_max_delay -from [get_ports {<input>} -to [get_ports {<output>}] <Tpd_Requirement>

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