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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

That's the way I wanted to avoid :cry:

I have to analyze 6 interfaces (MUX6:1)... probably every P&R run...

what kind of constraints can I actually make? I use no clocks, no registers in the path... TimeQuest is not really useful in this situation...

Thanks for the help so far...