IO constraints for buses routed through FPGA

They are surely a lot more than 1 ns. You can expect around 5 ns for each direction. This are mainly I/O delays that aren't affected by the fitter, so you will hardly achieve a considerably lower value.

However, I didn't suggest to make no constraints. I mentioned, that only tpd constraints are applicable. You have to find out, if they are helpful somehow.

Personally, I would start to check the delays reported by the timing analyzer without any constraints.