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Altera_Forum's avatar
Altera_Forum
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15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What you said makes sense if the delays of the FPGA are insignificant compared to the MOSI/SCK relation. My problem is I can't (don't know how to) trace the delays through the FPGA and I don't just want to assume they will be less than 1 ns... A constraint would spare me of these assumptions...